DDR-2 DRAM memory devices can use both the rising and falling edges of a clock to transfer read data to a memory controller. Given the frequency at which these data transfers can occur (i.e., 200-333 MHz and beyond) delays introduced by elements in the data path, such as interconnect and devices, can be comparable with the period of the clock. In other words, the delays associated with interconnect, devices delays, and the like can be equal to about one clock period where the clock frequency is 200 MHz or higher. These delays can contribute to complications in performing synchronous transfer of data from the DDR-2 memory to the controller.
In particular, it is known to use delayed versions of signals provided by the DDR-2-type memories (i.e., DQS/DQSN signals) to clock registers in the memory controller. Given the relatively large delays described above, the timing relationship between the DQS/DQSN clock signals and a system clock (i.e., SYSCLK) may be unpredictable especially given variations associated with process, voltage, and temperature. This unpredictable timing relationship between DQS/DQSN and SYSCLK may therefore make it difficult to pass data directly from the DDR-2 DRAM to the system that operates using a different clock.
It is known to use an additional resynchronization stage to resynchronize data received from the DDR-2 DRAM at the memory controller. Such an approach is described in, for example, “Overcoming DDR-2-Interface Challenges” by William Lau, EDN Magazine, Jan. 22, 2004, pg. 71-74.